¡û Supply source codes, You can copy in your site.!!
¡û Fast simulation with the dynamic memory allocation technique!!
¡û Written in VHDL only. No other software is requiered for simulation.
¡û Enable precise functional check
Timing violation detect
Read/Write access check
Refresh rate check
¡û And ... Reasonable price!!
¡ü Data initialize file read
¡ü Data dump to a file with signal trigger
Dump out all accessed address and current data at an arbitorary time
Cyberlabo Limited TEL 0427-39-7756 FAX¡¡0427-39-7757
Machida office: 1-9-5, Naka-machi, Machida, Tokyo, Japan 194-0021mailto: firstname.lastname@example.org..jp
Headquarter : 4-15, Wakamatsu-cho, Hadano, Kanagawa, Japan 259-1314