VLP80 (Variable Length Instruction Processor)

32 bit VLP80-32 / 16 bit VLP80-16


A Z80 binary compatible processor core implemented  with an efficient RISC architecture. Z80 commands are executed in fewer clock cycles,  the VLP80 is a high speed  Z80 equivalent. The VLP80 reads in instructions in 2 or 4 byte units and stores them in it's prefetch buffer. Therefore we do not need so many instruction fetch cycles and we increase processing speed.

No matter what the instruction length, 1 byte or 4 bytes, instructions are decoded in one clock cycle. Furthermore a 2 stage pipeline structure enables instruction execution to be carried out at the same time as instruction decode.

A new design of ALU allows most instructions to be decoded in one clock cycle, so Z80 CISC instructions are executed with the same efficiency as RISC instructions.
 

Features :

Performance :


Using a cross compiler we benchmarked our processor against HITACHI`s HD64180.

The results show our processor to execute more than 4 times as many
instructions per clock cycle as the HD64180 (both processors were
operating on a 4.9 MHz clock). Below are the times for a rather slow pi
calculation to 200 deciaml places.  

 HD64180    143 Sec.
 VLP80-16    34 Sec.

According to HITACHI there processor is 4.3 times faster than
the Z80. We estimate the Z80 would perform the same calculation in :

 Z80        630 Sec.

Package :

VHDL source code provided to user. We can also provide a netlist.

Circuit Scale:

On the order of 25,000 gates (depends on logic synthesis conditions).

Processing Efficiency:

On the order of 20~100 MIPS (depends on logic synthesis conditions).