Last modified 15 Apr. 2004
Our 16/32 bit Z80 binary compatible RISC CPU core model. Pipelined architecture
executes commands in fewer clock cycles. It can execute Z80 commands at
Please contact us for more details.
PCI Core Model
Behaivior model for PCI Target debug.Any access type is avairable.it's
contoroled by external file.No VHDL analyze required when
you modified data or address.
These cores are semi-custom model for synthesys.
PCI bridge VHDL model
PCI-PCI bridge(32-32,64-64,32-64), user sepcific
SDRAM controller with PCI interface
SDRAM contoroller for GIGA byte class memory system.
VITAL DRAM Simulatiom Model
We have available the following original VHDL simulation models.
All models feature :
Follow the following links for more information :
Pure VHDL code.(C code is not included)Fit for any VHDL simulator
Variable address size and Data Bus size.
VITAL timing and functions.
Capability to simulate any vendor's DRAM with adjustment of delay parameters.
Complete simulation model including refresh simulation.
User Specific Model:
We also are happy to make models meeting the specific needs
of a customer - (synthesizable or behavioural models).
Free VHDL models
We do not provide user support for these free models.
Comments are included in source code though.
question and firstname.lastname@example.org